Setting up Docker Image for SystemVerilog Workspace

Build Image with Dockerfile

docker build --tag sv_image:latest --no-cache .

Run the above PowerShell code with the following Dockerfile:

FROM ubuntu:24.04

ENV DEBIAN_FRONTEND=noninteractive
RUN apt update && apt upgrade -y
RUN apt install -y --no-install-recommends locales tzdata

# Set the locale to English (UTF-8)
RUN sed -i '/en_US.UTF-8/s/^# //g' /etc/locale.gen && locale-gen

# Set environment variables for English locale
ENV LANG=en_US.UTF-8
ENV LANGUAGE=en_US:en
ENV LC_ALL=en_US.UTF-8

# Set timezone to Hong Kong
ENV TZ=Asia/Hong_Kong
RUN ln -snf /usr/share/zoneinfo/$TZ /etc/localtime && echo $TZ > /etc/timezone

RUN apt update && apt install -y --no-install-recommends \
    make git curl ca-certificates python3 \
    build-essential pkg-config libz-dev \
    iverilog \
    verilator
RUN rm -rf /var/lib/apt/lists/*

RUN iverilog -V
RUN verilator --version

# Set up better PS1 prompt
RUN cat <<'EOF' >> /root/.bashrc

RED="\[\033[0;31m\]"
GREEN="\[\033[0;32m\]"
YELLOW="\[\033[0;33m\]"
BLUE="\[\033[0;34m\]"
MAGENTA="\[\033[0;35m\]"
CYAN="\[\033[0;36m\]"
WHITE="\[\033[0;37m\]"
BOLD="\[\033[1m\]"
RESET="\[\033[0m\]"

PS1="${GREEN}${BOLD}\u${WHITE}@${BLUE}${BOLD}\w ${MAGENTA}\$(date +%H:%M)${RESET} > "
EOF

RUN mkdir -p /workspace/sv/
WORKDIR /workspace/sv/

# Default shell
CMD ["/bin/bash"]

Start a Container

docker run -dit sv_image

# or mounting current working directory to the container:
docker run -dit --name sv_container -v ${PWD}:/workspace/sv sv_image:latest

Sample SystemVerilog Code

Source code counter.sv:

/*
 counter.sv
 */
module counter #(parameter WIDTH=4) (
  input  logic clk, rst_n,
  output logic [WIDTH-1:0] q
);
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= '0;
    else        q <= q + 1'b1;
  end
endmodule

Test bench code counter_tb.sv:

/*
 counter_tb.sv
 */
`timescale 1ns/1ps
module counter_tb;
  logic clk = 0, rst_n = 0;
  logic [3:0] q;

  // DUT
  counter #(4) dut(.clk(clk), .rst_n(rst_n), .q(q));

  // clock: 10ns period
  always #5 clk <= ~clk;

  // waveform dump
  initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, counter_tb);
  end

  initial begin
    rst_n = 0; repeat(2) @(posedge clk);
    rst_n = 1; repeat(20) @(posedge clk);
    $display("Final q = %0d", q);
    $finish;
  end
endmodule

Run Verilator

verilator -Wall --sv --timing --trace-fst --binary -o sim_verilator --top-module counter_tb counter_tb.sv counter.sv

./obj_dir/sim_verilator

Run Icarus Verilog

iverilog -g2012 -o sim.vvp counter_tb.sv counter.sv

vvp sim.vvp

You can put the output waveform file wave.vcd to VC Drom to conveniently check the results.